In the manufacturing process of a semiconductor device, various kinds of tests are carried out in each process and the test results are fed back in order to remove a defective product and to enhance yield. For example, an operation test to inspect whether the semiconductor device operates electrically normally and meets the specifications is performed, and only those that have passed the test are shipped.
As the circuit scale of an LSI increases, it is difficult to detect the internal operating state, and therefore, in order to detect the internal operating state, a scan circuit is formed. The scan circuit is a shift register in which flip-flop circuits (FF) are connected in the form of a chain and configured to output data of a logical circuit captured at a certain point of time to outside by supplying a clock to the FF. Normally, the scan circuit is formed by the FF used when the normal operation (system operation) is performed within the semiconductor device, however, there is also a case where the FF provided to form the scan circuit is used.
In the operation test of a semiconductor device, the test is carried out under environmental conditions set in accordance with the specifications, and also a predetermined test pattern is determined so as to check whether all the functions as to predetermined test items operate normally, and then, the test pattern is performed. In order to efficiently check the operations as to the predetermined test items, for example, in the case where there are portions capable of operating independently within the semiconductor device, by carrying out the tests by causing those portions to operate in parallel, the test time is reduced. As the number of circuits that operate in parallel increases, the load of the semiconductor device becomes higher.
The scan circuit has a number of FFs and the number of FFs operate simultaneously in accordance with the clock, and therefore, a large amount of current flows temporarily and the load of the semiconductor device becomes higher than that at the time of the normal operation. Because of this, a large voltage drop occurs in the power source supply circuit and noise occurs in accordance therewith, and there may be a case where the semiconductor device that does not cause any problem in the normal operation is determined to be defective by the test. The semiconductor device such as this should be originally regarded as a conforming product because it operates normally in the normal operation, and if such a product is regarded as a defective product, there arise such a problem that yield reduces.
Up to now, as a noise reduction circuit for removing noise that occurs when a power source voltage drops, the Schmidt circuit and the circuit that uses a CR filter are known, however, there has been such a problem that the maximum operating frequency is limited. Because of this, a noise reduction circuit for removing noise by inputting an input signal and a delayed signal, which is the input signal delayed by a delay circuit, to the logical gate is proposed. The proposed noise reduction circuit has two noise reduction circuits connected in two stages and has a function for preventing both the noise from the “high (H)” level to the “low (L)” level and the noise from the L level to the H level.